For semiconductor integrated circuits (chips) such as memory devices, it can be cost effective to include multiple product configurations in one base design. For example, it would be desirable for a device to be capable of accommodating multiple input and/or output data configurations.
While memory devices typically perform a like function—storing data values for subsequent access, various data input/output configurations have been proposed. As a first example, the rate at which data is accessed with a respect to a clock signal has given rise to single data rate type designs, in which data is accessed once per clock cycle, as well as double data rate (DDR) type designs.
Further, while some memory can be configured to operate according to a single clocking, others may operate according to double clocking. More particularly, some types of Quad Data Rate™ or QDR™ SRAMs (such as those manufactured by Cypress Semiconductor Corporation, of San Jose, Calif.) may be configurable for both single clocking and double clocking. In a single clocking configuration, input data are clocked into the device and out of the device according to a single clock. In a double clocking configuration, data can be clocked into the device according to one clock, and clocked out of the device according to a second, different clock.
As another example, to increase data throughput, data may be accessed in bursts (a sequential set of data values). However, burst length criteria may vary. That is, a burst length may be variable and/or data ordering for a given burst length can vary. As but two very particular cases, burst lengths may be two or four, while burst ordering may be linear, “interleaved”, or some other user designated order.
Conventionally, an integrated circuit may be manufactured to accommodate a given input and/or output configuration by a permanent manufacturing option. Bond and/or metal options may be used to generate appropriate control signals for accommodating a given burst length and/or data ordering. As is well understood, a bond option may be an option in the way input signals are applied to an integrated circuit die (typically by way of bond pad). A metal option can be an option in an integrated circuit metallization layer.
However, conventionally, it can be difficult to design a simple and flexible scheme that can meet a wide variety of device options.
To better understand various aspects of the disclosed embodiments of the invention, a conventional data input path and output path will now be described.
A conventional approach to a data input path (DIN PATH) is shown in FIG. 15, and designated by the general reference character 1500. A conventional data input path 1500 can include eight registers (M/S REG), including a lower four registers 1502-0 to 1502-3 and upper four registers 1502-4 to 1502-7. Input data (DIN) can be serially shifted through the lower four registers (1502-4 to 1502-7) according to input clock edges (k/kb). Next, data in lower registers (1502-0 to 1502-3) can be loaded in parallel into upper registers (1502-4 to 1502-7) according to an enable signal en. Upper registers (1502-4 to 1502-7) can be “late-write” registers, for subsequent writing of input data into a memory core.
A conventional approach to a data output path (DOUT PATH) is shown in FIG. 16 and designated by the general reference character 1600. A conventional data output path 1600 can include a four-stage shift register 1602 and an output latch 1604. Shift register 1602 can include registers 1606-0 to 1606-3 connected in series by load/shift multiplexers (MUXs) 1608-1 to 1608-3. Data output path 1600 can also include data MUXs 1610-0 to 1610-3. Each data MUX (1610-0 to 1610-3) can receive core data or match data. Core data (core_data) can be data received from a core portion of a memory device. Match data (match_data) can be data present in an input stage (from a write operation, or the like) that is being read before being written into a core portion. Data MUX 1610-0 can provide data to register 1606-0, while data MUXs 1610-1 to 1610-3 can provide data to load/shift MUXs 1608-1 to 1608-3, respectively.
Data from data MUXs (1610-0 to 1610-3) can be loaded in parallel into registers (1606-0 to 1606-3). Such data may then be serially shifted to output latch 1604 according to clock signals. In FIG. 16, data may be shifted according to clock signals k/kb. Data may be output from output latch 1604 according to output clock signals c/cb. FIG. 16 thus shows a double clocking arrangement.
Both the conventional data input path and the conventional data output path can have drawbacks. In particular, such approaches can lack flexibility in accommodating various data clocking configurations. In particular, both approaches have limits to the order in which data are input to a write path, or output from a read path. Further, such approaches may not be suitable for accommodating multiple functions, such as variations in clocking type (e.g., single or double), or multiple burst lengths, as data values may only be sent in a fixed sequence.
In light of the above, it would be desirable to arrive at a data path arrangement that is relatively simple to implement.
It would also be desirable to arrive at a data path arrangement that can flexibly accommodate multiple functions (e.g., data clocking types, burst lengths, burst sequences). It would also be desirable for such an arrangement to be accomplished via a relatively simple process step, in contrast to having to design entirely new circuits for each such variation.